Antyakula ramesh Ramesh

Design For Testability at nvidia

• India - Bengaluru
• January 2014 to September 2014

Worked in a IEEE1500 test standard protocol Design, writing complex test suites or regressions, tcl scripts to support the devolpment of the design. These regressions include different clock evaluation based on context, wrapper boundary register(WBR) insertion, WBR-analysis, WBR-validation, scan requirement, scan violation check etc.
2. I was Creating regressions for various checks for validating DFT flow with good coverage and storing the generated report in the golden directory for future reference .The Checks include : Multiple driver check, clock resolution, Scan Debug check, validation of DFT in scan mode, validation of DFT in scan in by_pass mode, validation of DFT in scan compression mode, validation of DFT in scan compression with by_pass mode, chain extraction in partition, Grouped scan blocks check, Pipeline blocks check, chain extraction of partition with compressed mode, scan violation etc. Created around 60-70 regressions covering different aspects of DFT.
3. Running and debugging DFTValidation checks and scan insertion flow on various chips(CPU’s, GPU’s) at various modes and verifying that run is clean, no differences.
4. Debugging C++ and TCL programs.
5. Writing TCL scripts, xml and yaml scripts to assist in the enhancement of EDA tools.
6. Validating I1500 flow in various chips(CPU’s and GPU’s).


Computer Skills :

S/W Languages: C, C++ basics, python Script, perl, tcl, data structures, Algorithms.. H/W Languages: verilog, vhdl, SV(basics).
Operating Systems: windows, linux.
EDA tools : modelsim, cadence(Virtuoso schematic Editor, Virtuoso layout Editor, Analog Design Environment, Assura), tanner, LTspice, Quartus, xilinx, Icarus, Verdi.
DFT tools: DFTAdvisor, FastScan, TestKompress, Etchecker .