Hemant Juneja

INTERN at IIT

• India
• My current job since August 2020

Project Details: Implementation of low power Healthcare SOC based on RISC-V core.
Learnings:
* New low power techniques at both front and backend.
* Architecture of UART, System bus and interconnection bridge.
* Logic Synthesis of HDL into gate level netlist and perform PnR Flow.
Responsibility:
* To define specifications for UART suitable for SOC.
* To design Architecture and HDL of UART.
* To implement a low power technique at the backend level.
* To perform logic synthesis using SCL180nm PDK on Synopsys design compiler.
* To perform PNR on a synthesized design using IC compiler by Synopsys.
* To generate a DRC/LVS clean layout without any timing violations.
TOOLS AND LANGUAGES DETAILS:
 Synthesis Tool : Design Compiler.

at VLSI Expert Pvt. Limited

• India
• February 2020 to July 2020

at Verilog

• July 2017 to November 2017

TCL, BASH & Perl
 CMOS
 Digital electronics.
 Analog electronics.
* Embedded System using PIC and ARM Microcontroller | KVCH (Noida) | (