Engineer R & D
Tejas Networks Ltd
مجموع سنوات الخبرة :10 years, 11 أشهر
20 months of strong experience in research, analysis, design and verification of modules in Verilog. Expertize in FPGA design, simulation and their functional verification on target boards.Worked on different interfaces such as LPC, I2C, SPI etc. Performed timing analysis for many inerfaces. Debugged critical issues related to board design, FPGA design and provided support to other teams. Industrial experience in a product based networking company provided an opportunity to participate in customer demonstration and product deployment.