hardware engineer
IBM
مجموع سنوات الخبرة :10 years, 9 أشهر
Simulated DDR2 topologies with Hspice
Simulated PCIe and Xaui high speed buses with Hspice and Cadence tools
·Created board routing rules and communicated them to the physical layout team
In charge of the electrical charaterization of the processors.
Simulated DDR2/DDR1 topologies
- Responsible for DDR2/DDR3 Characterization
- Validated Platform silicon Designs.
- Designed new card for to debug critical CPU timing issues
Responsible for developing new cards for debugging dual core Processors
- Drive schedules and budgets for new designs
- ROI analysis
-Outsourcing of design projects to meet critical production schedules
• Developed and implemented a strategy to eliminate unutilized tool licenses to reduce cost.
• Negotiated pricing of components and licenses with 3rd party vendors.
• Coordinated with marketing to define road map for automation products designed for server and network.
• Reduced external accounting fees and increased access and availability of business information.
• Responsible for supplier selection, negotiations, benchmarking, financial analysis, transition efforts and performance.
• Provided assistance to teams in the design, the simulation and the board layout of Intel-based Mother- boards.
• Managed and maintained model libraries of third-party vendors to assure a high level of model accuracy.
GPA 3.9
GPA 3.5
GPA 3.5