Martin Casabella

Security IP cores and complex subsystems digital hardware architecture and design. Accompanying the development of the product through the entire lifecycle, from customer interaction, definition, implementation and verification

Design, simulation, verification and implementation of novel DSP architectures for next generation data center interconnect. Design optimizations for low
power, complexity, area reduction, high performance or any other needed requirement.

Research and development specializing in the design of Field Programmable Gate Array integrated circuits.

Two projects were implemented:

Alternative methodology to efficiently implement two-dimensional convolution that outperform FPGA in terms of both memory and performance. Dynamic memory reuse was accomplished, with a linear increase in memory utilization with respect to parallelism level


Reduced complexity adaptive equalizer for compensating the transmitter I/Q time skew and the phase and gain errors of the optical modulator, in subcarrier multiplexing (SCM) receivers. Drastic complexity reduction was achieved, up to four times less than existing similar solutions together with important performance improvements.