Mayank sharma

Trainee Engineer at UMAYA Softech Pvt. Ltd

• India - Agra
• May 2011 to July 2011

: Analysis of Signal and controlling of Railways.
• Two month training on VHDL.
Learning basic tools of VHDL.

• to

Academic Project Works
• Design and Analysis of CMOS Based Low Power CSA (June’15 - May’17)
Project based on Low power and less delay in Carry Select Full Adder by using various Technique using Cadence
Virtuoso. On the basis of this modification of 4-bit and 8-bit CSLA architecture, it has been developed and compared
with the conventional CSLA architecture. The proposed design has reduced area and power as compared with the
conventional CSLA with the minimum amount of delay. This work evaluates the performance of the proposed
designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and
layout in 180nm. In this work we have presented systematic approach to construct full adders using conventional,
10T, transmission gates (TG) and binary to excess converter techniques (BEC). The results analysis concludes that
the proposed CSLA (Carry Select Adders) structure is better than the normal regularly used CSLA (Carry Select
Adders).
• Design of UART Using VHDL(August’11 - may’12)
Project Based on Serial to Parallel or Parallel to Serial converter & to act as MODEM (Modulator/Demodulator)
using VHDL Language. In which the data format and transmission speeds are configurable. The electric signaling
levels and methods are handled by a driver circuit external to the UART. A UART is usually an individual (or part of
an) integrated circuit (IC) used for serial communications over a computer or peripheral device serial port.
• Midnight Security Light ( October’11-November’11)
To sense the sunset and turn on the LED and to open the light (bulb) automatically by gate terminal of TRIAC is
high.