محمد Sarwar

•Supporting following tools:
1. DFT Compiler
2. Tetramax

•Successfully resolved 130+ issues involving customers from USA and Asia Pac in last 3 quarters.

•Possess strong hold into following areas:
1. Scan Testing,
2. Top Down Scan Insertion,
3. DFT Design Rule Checks (DRC) and Fixing,
4. Exporting Design Files,
5. High Capacity DFT flows,
6. DFTMAX (Compression Technology),
7. Controlling ATPG,
8. Minimizing ATPG patterns and Debugging Low Coverage,
9. Transition ATPG,
10.Timing Exceptions and
11. Diagnosing ATE failures.

•Solvnet Author for following articles
1.“How to Generate a Transition Fault Pattern for a Particular Clock Domain?” - - Doc Id: 035555
2. “How can I get a list of all X cells from the analyze_compressors command?” - -Doc Id: 037876
3. “How to control excessive capture switching during Power-Aware ATPG?” - -Doc Id: 038632
4. “How to Apply the write_scan_def -expand_elements Option to All CTL-Modeled Cores?” - -Doc Id: 038634

•Implement Scan Insertion on the netlist received from synthesis team.
•Take scan inserted netlist for ATPG and estimate test coverage.
Tools used: DFT Compiler and Tetramax.

My contribution includes
•Create ATPG setup for StuckAT scan and Bridging patterns. Complete Gate level simulations with timing for the same.
•Generation of .bsd file and testbench for JTAG simulations.
•Understand strategy and develop testcases performing Frequency BIST of clock generators.
•Compile and use latest RTL database for the DFT simulations.
•Giving feedback to client at the right time for each milestone achieved.
•Pattern handoff to the tester team.
Tools used: Tetramax, Ncsim, Simvision and Client specific internal tool.

My contribution includes
•Programming the respective clock generators at functional frequency and make sure that Memory BIST is happening at this functional frequency.
•Interact with ATE team on debugging pattern failures on tester.
•Generation .bsd file and testbench for JTAG simulations.
•Understand strategy and develop testcases for Observation and Frequency BIST of clock generators.
•Giving feedback to client at the right time for each milestone achieved.
•Pattern handoff to the ATE team.
Tools used: Tetramax, Ncsim, Simvision and Client specific internal tool.

My contribution includes
•Develop Smart testcases performing Frequency BIST and clock observation of Clock generators available for the SOC.
•Deliver Frequeny BIST vector to ATE team and make sure it passes on Tester.
Tools used : Ncsim, Simvision.