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Muthyala Reddy, Design Verification engineer

Muthyala Reddy

Design Verification engineer

UST GLOBAL SEVITECH SYSTEMS

Location
India - Cuddapah
Education
Bachelor's degree, Electronics And Communication Engineering
Experience
2 years, 3 Months

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Work Experience

Total years of experience :2 years, 3 Months

Design Verification engineer at UST GLOBAL SEVITECH SYSTEMS
  • India
  • January 2021 to March 2023

Education

Bachelor's degree, Electronics And Communication Engineering
  • at sree vidyanikethan engineering college
  • March 2020

Specialties & Skills

Design
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Hardware Verification
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SoC
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IP design
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Semiconductor Design
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Digital electronics , Verilog, System Verilog, UVM, Python, C and C++ languages, Perl scripting
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Social Profiles

Personal Website
Personal Website

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Languages

English
Expert

Training and Certifications

Advanced VLSI design and verification (Certificate)
Date Attended:
January 2021
Valid Until:
January 2022