Rajesh Panda

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PROECT NAME : Fast Locking CPPLL
SOFTWARE - : Cadence Virtuoso(Spectre)

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PROECT NAME : Fast Locking CPPLL
SOFTWARE - : Cadence Virtuoso(Spectre)
OS - : Linux
PROJECT DESCRIPTION :
The frequency synthesizer which is a main functioning block of wireless transreceiver is based on charge pump PLL. Speeding up the synthesizer's locking process can be achieved by speeding up the charge pump PLL means the settling time of control voltage.
RESPONSIBILITY :
Developed the total charge pump PLL structure by building schematic diagrams and verifying the individual blocks output like PFD, CP, VCO etc. Suggested a novel PFD structure and BBFC structure to minimize the effective locking time of CPPLL.
(2) PROJECT NAME : 1x3 ROUTER
SOFTWARE : Xilinx ISE, Questa sim & Gvim editor
HDL : Verilog, UVM
PROJECT DESCRIPTION :
Router is a device that forwards data packets between computer networks. It The router accepts on a single 8-bit port called Data and routes the packets to 1of 3 output channels.
RESPONSIBILITY:
Design various building blocks of Router by Verilog HDL. Developed Verilog test bench for the same. Calculated code coverage . Verified the design by writing different test cases through UVM methodology hierarchy.
(3) PROJECT NAME : Serial Peripheral Interface master core
SOFTWARE : Questa sim & Gvim editor
HDL : UVM
PROJECT DESCRIPTION :
A serial data link standard named Serial Peripheral Interface is verified using UVM. This protocol demonstrates the ability to transform incoming parallel communication from a wishbone bus, into serial communication that is being transferred using the SPI protocol. Serial Peripheral Interface (SPI) is Serial synchronous interface that facilitates the transfer of synchronous serial data in full duplex mode .