Physical Design Engineer
Pozibility Technologies
Total des années d'expérience :6 years, 5 Mois
Designing the backend domain of the semiconductor chip and verifying with all the checks before the production phase. The job role includes designing the sub blocks of the chip which include Synthesis, Floorplan, Placement, CTS, PostCTS, Route, PostRoute, STA, DRC, LVS, LEC, PV.
To work on a project in digital domain using verilog code in Xilinx 14.7 and providing the simulation results on ModelSim simulator.
Second PUC with physics, chemistry, mathematics and biology combination
From 5th-10th grade
From 1st-4th grade