Senior Manager, Engineering
Illumina INC
Total years of experience :24 years, 5 Months
New product Introduction and On market supplier enabling and sustaining - reagents, plastics, flowcells and semiconductor devices
•Managing Illumina's suppliers across reagents, plastics, semiconductors, and flow cells for On-Market product sustaining. Technical ownership of supplier issue resolution in high volume manufacturing, enabling alternate source selection and qualification, and managing overall technical relationships with broad range of supply base.
•Managing supplier risk and cost reduction efforts to improve profit margins and reduce overall consumable expenses in conjunction with supply chain and supplier quality teams
•Develop best known methods, standardized operating procedures and processes to enable supplier down selection, supplier development and qualification
•Resolve manufacturing and process issues in high volume manufacturing to maintain Illumina’s supply chain integrity while reducing operational cost
TECHNOLOGY DEVELOPMENT LEAD - Next-Generation PCB, substrate Technology & advanced packaging
•Over 13 years of experience leading, managing, and integrating activities of multidisciplinary teams to enable next generation product roadmap, substrate technology, and advanced packaging development, including application processors, mobile station, and data modems, across the globe from Asia to Europe
•Supplier quality management through spec definition and authorship, issue resolution, line audits and definition of line control plans/RFCs. Experience in resolution of multiple quality issues in high volume manufacturing across full spectrum of substrate manufacturing processes through assembly and package reliability
•Responsible for Supply chain enablement and process pathfinding, development and implementation with substrate suppliers and assembly sites with focus on manufacturing and design rules, yield improvement through manufacturing process optimization, DOE planning and execution, finer pitch routing, improved alignment targets, lower plating tolerances, and material development for lower roughness interfaces for improved electrical performance
•Technology Roadmap development and setting: Substrate technology development across all substrate technology modules. Driving industry for Line pitch, Via, via alignment and package substrate architecture.
•Substrate Technology team manager, with direct reports managing projects spanning technology development, Design for manufacturing review, New product introduction, Quality management in High volume manufacturing and spec. authorship
•Support sourcing team in developing strategies for qualification and leveraging technical skills to support pass-through pricing application to reduce overall costs with substrate and assembly materials, and enabling alternate material and substrate sources by negotiation and qualification
•Lead for PCB and Substrate Patterning process innovation and development including lithography, plating, etching and metal roughening.
•Develop new surface finishes to enable new flip chip bonding technologies and reliability requirements; Focus on FC-CSP laminates, bare die PoP packaging, FCBGA substrate process development, and substrate/assembly package interactions
10 years of experience in driving and collaboratively integrating activities of cross-functional teams, to evaluate technical feasibility of new substrate architectures though package development platforms, from pathfinding, to manufacturing technologies and processes design and development, supply management, and quality control
•Drove collaborative efforts with material suppliers for material development and enabling and drove substrate suppliers for testing and implementation; led several task forces and collaborated extensively with assembly manufacturing teams on activities across different platforms and product segments to trouble shoot, identify and resolve substrate manufacturing, and substrate assembly interaction problems in desmear, electrolytic Cu Plating, Dielectric to copper adhesion, Surface Finish, and Flip Chip/BGA solder joint reliability, second level joint integrity
•Led the development and startup of a new manufacturing facility, from feasibility analysis, engineering and layout, to capital equipment and technology selection, and installation, for a full manufacturing line across several disciplines; led the wet area team, customized fourteen (14) wet equipment sets, managed all design and install activities.
•Managed the development of Halogen free materials, worked with internal customers and stakeholders to certify and implement new materials for improved reliability while maintaining Intel’s environmental leadership
•Generated innovative substrate manufacturing techniques and secure Intel Intellectual Property through invention disclosures (fifteen (15) published patents and three (3) in preparation)
•Organic substrate engineering: focused on High Density Interconnect and Molded Matrix Array Flip Chip packages
•Substrate Metallization Core Competency: driving Cu plating (electroless and electrolytic), surface finish, wet etching, Cu to Dielectric adhesion promotion, Dielectric desmear and wet chemistry modules focused on Flip Chip Substrate manufacturing; duties include Pathfinding and Development lead on related modules
•Substrate Materials Core Competency: driving Core, dielectric build up and Solder Resist Pathfinding and development to identify and enable next generation materials to meet manufacturing and reliability standards for Flip Chip packages
Biotechnology and surface modification Applications
•Biological applications: Experience working on new technology for biomimetic nanomaterials that can replace natural enzymes for sensing applications using regenerative catalytically active thin films and ultra-smooth surface coatings using RNA in thin films
•Synthesized, designed, and constructed various monomeric and polymeric compounds and thin films for ionic species separation and exchange membranes, and polymer and macromolecule exchange
•Worked on enhancing ion chromatographic functionality by modifying ion exchange resin surface properties with polyelectrolyte multilayers
•Worked on ion templating and diffusion control of charged species based on ionic charge with polymeric thin films
•Developed a diffusion model for charged macromolecules and Studied the impact of film and environmental variables on polymer-polymer diffusion and interaction, using Neutron Scattering (NIST NCNR)
•Deeply versed in a wide array of thin Film and material characterization techniques including Size Exclusion Chromatography-Multi-Angle Light Scattering and Quasi Elastic Light Scattering; Fourier transform Infrared Spectroscopy FTIR, Attenuated total reflectance FTIR, and Continuum microscope FTIR spectroscopy; UV-Vis Spectroscopy, Raman Spectroscopy, Surface Characterization: (Profilometery, Ellipsometery, Static Contact Angle, AFM, XRF), Wet Chemistry (Electrochemistry (Cyclic Voltammetry, Chronoamperometry), Atomic Absorption, Atomic Emission, High Performance Liquid Chromatography)
REPRESENTATIVE PUBLICATIONS and patents
Below are representative publications and patent titles; these were in collaboration with many esteemed colleagues. More information can be provided upon request.
Patent subjects: Removing dry film resist residues using hydrolyzable membranes; Microball placement solutions; Alternative to desmear for build-up roughening and copper adhesion promotion; Routing layer for a microelectronic device, microelectronic package containing same; Selective electroless plating for electronic substrates; Method of removing unwanted plated or conductive material from a substrate, and method of enabling metallization of a substrate using same; Method of enabling selective area plating on a substrate; Coreless substrate and method of manufacture thereof; Integrated circuit and process for fabricating thereof; Optical die structures and associated package substrates; Substrates for optical die structures; Method of manufacturing a substrate for a microelectronic device, and substrate formed thereby
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