Kareem Elazhary

Developed a MIPS dual-core pipelined processor with a 512 bit direct mapped instruction cache and a 1Kbit
two-way associative data cache using SystemVerilog on an FPGA (Altera DE2 Board).
Steganography in Python Spring 2016
• Implemented a steganography GUI using PyQT to encrypt and decrypt text and image messages into an image
medium using NumPy to perform the bit manipulations.
ASIC Design: Edge Detection using an FPGA (Image Processing) Spring 2016
• Developed an Application Specific Integrated Circuit (ASIC) to implement the Sobel edge detection algorithm
on images using SystemVerilog. Observed a 300% improvement compared to python code. The project was
implemented on a DES2i-150 board using Quartus and Qsys.