Verification Team Leader
ST MICROELECTRONICS
مجموع سنوات الخبرة :16 years, 5 أشهر
Our last project consist on new imager dedicated to Nokia mobile phones. I'm the team leader on the verification activity. It includes functional, mixed and FPGA verification.
Digital Verification Engineer - Technical Leader
Chip 9600: SoC for Smartphone 4G ST-ERICSSON - FPGA prototyping
- Chip compilation and elaboration. Adapt IPs for FPGA prototyping constraints.
- Booting the chip and debugging the list of regression.
- Giving feedbacks on design and improving the hardware/Software quality.
- Technical management and reporting.
Technical Environment: QuestaSim, Clearcase, VHDL, Verilog, C.
Functional Verification Engineer
Chip 9600 : SoC for Smartphone 4G ST-ERICSSON - FPGA prototying
- Developing integration's verification tests for IPS SPI, UART, Muti-Timers, IrDA and IRRC.
- Participation in development of generic and modular verilog Test bench.
- Supporting verification teams on new project using Tester USB 2.0 OTG.
Technical Environment :
QuestaSim, NCsim, Clearcase, VHDL, Verilog, C.
Functional Verification Engineer
Chip 7600 : SoC for mobile phone 4G ST-ERICSSON
- Development of integration tests for ARM Cortex A11, USB, DMA, UART and Memories Controllers FSMC
- Improving Test bench structure and Verification IP generation flow.
- Setting a new verification specification of new IP USB 2.0 OTG.
- Development a new verilog Denali USB tester and software for booting USB IP.
- Supporting integration team to solve RTL bugs and validate hardware patches.
Technical Environment :
QuestaSim, NCsim, Clearcase, VHDL, Verilog, C.
Chip M700 : SoC for 4G Communication Keys ST-ERICSSON
- Development and update of functional and integration tests for IPs Coresight, AXI bus, Memory controller ARM PL35x, Security bloc HAM and Fuses.
- Hardware/Software bug tracking.
- Supporting both Integration and Timing Analysis Teams to produce specific tests.
- Testbench update.
- Gate-level debug for Coresight IPs
Technical Environment :
QuestaSim, Clearcase, Eclipse, VHDL, Verilog.
Engineer Graduate Internship
Chip STB7111 : Smart TV Core (1.4M Gates)
ARM9, Duo-Core Architecture
- Specification of Transactional Level Modeling (TLM) verification IPs.
- Implementing of two new TLM verification IPs : UART and I²C.
- Improving of a new platform of regression by implementing sequential and parallel test runner.
- Validation of a new internal verification tool of "non-regression"
Technical Environment :
VHDL, SystemC, NCSim, PERL, Tck/Tk.
Engineer Internship - FPGA prototyping.
WIMAX Repeater 802.16 : chip for 4G communication
- Definition of a new product of 4G repeaters.
- Technical specification of the chip and requirements for digital IP signal processing.
- Prototyping and characterization of the circuit using FPGA Cyclone II.
Technical Environment :
QuartusII, ADS.
2005-2008 ENSERG ( School of Microelectronics Engineering, Grenoble - France), Master's degree of Scientific and Executive Engineering. Major: Microelectronics, Computer Science and Nanotechnologies.
2003-2005 IPEST (Preparatory School of Science and Technology, Tunisia), a specific 2 year undergraduate program leading to a very competitive national examination to the French engineering Schools "Grandes Ecoles", specializing in mathematics and physics.
2002-2003 Scientific Baccalaureate, Mathematics Major, Highest Honors, Lycee Ibn Rachiq, Ezzahra, Tunisia.