ABIDAR Jamal, CTO

ABIDAR Jamal

CTO

Personal Project

Location
United Arab Emirates - Dubai
Education
Master's degree, Electrical engineering
Experience
10 years, 4 Months

Share My Profile

Block User


Work Experience

Total years of experience :10 years, 4 Months

CTO at Personal Project
  • United Arab Emirates - Dubai
  • June 2015 to May 2016

Chief Technology Officer for a mobile application project

• Project Management and Realization of a mobile application on Android/iOS with a Google Cloud backend(In Progress)
• Requirements gathering, Specifications, UI/UX design using Sketch3 (Completed)
• Prototyping using Invision (Completed)
• Development & Testing of the apps using Android Studio/Xcode (In Progress)
• Development & Testing of the web app (RESTful API) on Google Cloud Platform using Android Studio (Planned)
• App Store Optimization (ASO) and A/B testing(Planned)
• Alpha/Beta Testing (Planned)
• Internet site & Landing page development (Planned)
• Mobile analytics and Crash analytics (Firebase) (Planned)
• SEO, Digital Marketing (Facebook, Twitter, Pinterest, Instagram, Youtube …) and Growth Hacking (Planned)

Expected delivery on December 2016 for Android and June 2017 for iOS.

Principal Digital Hardware Engineer (Research & Development, IT, Security) at GCSS - Abu Dhabi
  • United Arab Emirates
  • July 2008 to June 2015

Providing technical expertise, mentoring and support to the Hardware team (HW) for the development of FPGA based prototypes.

Block Cipher Testing Platform:
• Specification (High Level Specifications and Detailed Specifications)
• Design (Hardware & Software Design documents)
• Implementation documentation
• Development in VHDL and C languages (Altera FPGA and bare metal software)
• Symmetric Cryptography: AES, DES, 3DES and locally developed algorithms
• Testing and throughput measurements
• Demos to top management and customer

True Random Number Generator:
• Specification (High Level Specifications and Detailed Specifications)
• Design (Hardware & Software Design documents)
• Implementation documentation
• Development in VHDL and C languages (Altera FPGA and bare metal software)
• State of the art of True Random Generation Algorithms by reading research papers and standard recommendations from NIST (NIST SP 800-90A)
• Selection of the most suitable algorithm
• Implementation, Testing and Performance measurements
• Security testing using NIST testing evaluators (Die Hard & NIST SP 800-22)
• Demos to top management and customer

File Encryption:
• Specification (High Level Specifications and Detailed Specifications)
• Design (Hardware & Software Design documents)
• Implementation documentation
• Development in VHDL and C languages (Altera FPGA and bare metal software)
• Symmetric Cryptography: AES, DES, 3DES and locally developed algorithms
• Implementation, Testing and Performance measurements (TCP/IP, Wireshark)
• Demos to top management and customer

USB Encryption:
• Specification (High Level Specifications and Detailed Specifications)
• Design (Hardware & Software Design documents)

Line Encryption:
• Specification (High Level Specifications and Detailed Specifications)
• Design (Hardware & Software Design documents)
• Implementation documentation
• Ethernet Encryption
• Development in VHDL and C languages (Xilinx FPGA and bare metal software)
• Symmetric Cryptography: AES, SERPENT, DES, 3DES and locally developed algorithms
• State of the art of Side Channel Attacks & Countermeasures by reading research papers
• Implementation of counter measures against Side Channel Attacks
• Implementation, Testing and Performance measurements (TCP/IP, Wireshark)
• Demos to top management and customer

Cryptographic Board:
• Specification (High Level Specifications and Detailed Specifications)
• Design (Hardware & Software Design documents)
• Implementation documentation
• Ethernet Encryption, VPN, Storage Encryption and USB Encryption
• Development in VHDL and C languages (Altera FPGA and Linux OS)
• Development of a Linux driver for a custom VHDL component
• Overseeing the development of Secure booting process, FPGA modules and Linux driver/application
• Interfacing with PCB provider for technical topics
• Implementation of counter measures against Side Channel Attacks
• Implementation, Testing and Performance measurements (TCP/IP, Wireshark)

Project Manager (Research &Development, IT, Security) at GCSS
  • United Arab Emirates - Abu Dhabi
  • June 2012 to June 2015

Project coordinator for the Hardware Team (HW) for the Line Encryption and Cryptographic Board projects.

• Creation of Project Charters, Stakeholder management strategies
• Requirements gathering and creation of Scope statement
• Determining Time and resources required to complete the projects
• Identifying (WBS) and Scheduling the activities to successfully complete the projects
• Consulting the Team and the management when necessary
• Overseeing the implementation phase with weekly meetings and creation of weekly/monthly status reports
• Monitoring and controlling the technical work (Actual vs Planned)
• Technical documentation writing and overseeing (High Level Specifications, Detailed Specifications, Design document, Implementation documentation, Unit Test documents, Integration Test documents, System Test documents)
• Technological surveillance on Hardware Security (Symmetric Cryptography, Attacks and Countermeasures), FPGA technology and Security Evaluation Standards (FIPS 140-2, NIST SP 800-90A, Common Criteria)
• Participating in the redaction of an RFP to select a PCB manufacturer for the crypto board project
• Team mentoring on Hardware Security topics and System Development
• Management and Customer presentations

Project Manager (Research &Development, IT, Security) at GCSS - Abu Dhabi
  • United Arab Emirates - Abu Dhabi
  • July 2012 to June 2014

Project coordinator for the Hardware Team (HW) for the Line Encryption and Cryptographic Board projects.

• Creation of Project Charters, Stakeholder management strategies
• Requirements gathering and creation of Scope statement
• Determining Time and resources required to complete the projects
• Identifying (WBS) and Scheduling the activities to successfully complete the projects
• Consulting the Team and the management when necessary
• Overseeing the implementation phase with weekly meetings and creation of weekly/monthly status reports
• Monitoring and controlling the technical work (Actual vs Planned)
• Technical documentation writing and overseeing (High Level Specifications, Detailed Specifications, Design document, Implementation documentation, Unit Test documents, Integration Test documents, System Test documents)
• Technological surveillance on Hardware Security (Symmetric Cryptography, Attacks and Countermeasures), FPGA technology and Security Evaluation Standards (FIPS 140-2, NIST SP 800-90A, Common Criteria)
• Participating in the redaction of an RFP to select a PCB manufacturer for the crypto board project
• Team mentoring on Hardware Security topics and System Development
• Management and Customer presentations

Design and Development Engineer (Research & Development, IT, Defense) at THALES COMMUNICATION - Paris
  • Other
  • January 2008 to July 2008

Responsible for the development of the mode5 security and interface components for the TSC2002 IFF transponder (Identification Friend or Foe).

• Study and review of the mode 5 specifications and design documents (DO-178B)
• Development and testing of the HDLC, CRYPTO and TSC software components
• Testing the software implementations
• Profiling the software implementations
• Performance reviews and improvements
• Technical documentation writing (Implementation document)

Support and Development Engineer (Research & Development, IT, Telecommunications) at SAGEM - Paris
  • Other
  • January 2007 to January 2008

Responsible for the 3G SyncML and PIM software components of my850C and my600X products.

• Study and review of the SyncML and the 3G Ericsson Mobile Platform (EMP)
• Bug search and reproduction
• Peer reviews for team members
• Software evolutions development and bug corrections for the SyncML component (C language)
• Over the air frame analysis for bug detection using Ethereal
• Design and development for JSR75 compliance (Java Specification Request75)

Design and Development Engineer (Research & Development, IT, Transportation) at CS - Paris
  • Other
  • February 2006 to January 2007

Responsible for the “sleep mode” sub system and the maintenance applications of the Motorway Emergency Calling System.

• Benchmarking and choice of the low consumption microcontroller
• Specification, design, development and testing of the “sleep mode” microcontroller application
• Schematics and printed circuit board (PCB) design review for the whole system including an FPGA and a microcontroller
• Development of the local maintenance application (C language and Linux I/O management on an FPGA)
• Development of the remote maintenance application (Server side: C language, CGI Scripting, Apache server and Client Side: HTML/CSS)
• Technical documentation writing (Specification, Design document, Implementation document, Unit and Integration test reports)

Education

Master's degree, Electrical engineering
  • at ECE Paris
  • September 2005

Specialties & Skills

Security
Project Management
Hardware
Software
Technical Consulting

Languages

French
Expert
English
Expert
Arabic
Beginner

Training and Certifications

PMP (Certificate)
Date Attended:
December 2013
Valid Until:
November 2016