Zia Ahmed

Achievements:

• Built custom solutions specific to Design Enablement.
• Architected standard reference data of Design Manuals, & IP. And help digitize them
• Designed UI/Interface for Digital Product Catalog, IP Catalog (customer portal)
• Solution Architect for Configurator which could be extended to CPQ (Configure Price Quote)
• Led Custom Content management solution for PDK (Physical Design Kits) etc.
• Brought Cost savings of $600K by replacing licensed app by building in house app in 2020.
• Brought Cost Savings of $3.5M by unifying & optimizing Tapeout process. Design Tape-In DB to
Mask (for Wafer) cycle time reduced from a week to 2 Days.

Responsibilities:

• Stakeholder engagement and business leaders’ alignment for transformation goals.
• Design develop and deliver applications for IP, Tapeout, Process Technology and PLM on time
• Conduct Training for successful adoption to end users.
• Prioritize, and manage transformation programs and technology projects, partner with key business
stakeholders
• Lead delivery managers, program/project managers across the globe, 6 employees and offshore
professional services of 20 FTE.
• Manage commercial arrangements with technology software partners and professional service
providers.

Achievements:

• Completed first successful engagement in the AP for AMS & enabled their adoption in the region.
Responsibilities
• Provide technical customer support, training & consultant for the APAC region in Analog Mixed
Signal tools of Synopsys.

Achievements:

• Helped team for a successful tape out of First RF Smartcard Chip in ST Singapore
• Awarded Employee of the QTR for Developing RF Smartcard

Responsibilities

• Work on EDB sponsored for EZ Link card development. EZ link card was a RF Smartcard meant for
use in local Transport for touchless payments.

Senior Design Engineer (India) Jul 1998 - Jun 2001

Achievements:

▪ For 8D corrective action, developed methodology to capture missing Vias in Ebeam Probe Pads

Responsibilities

▪ Automation of Full Chip IP Design for optimum placement of STD cell IP’s for min Silicon area
▪ Testchips Failure detection system development.
▪ Standard Cell Testchip Wafer level measurement