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RESEARCH THESIS An FPGA Implementation of Video Enhancement Algorithm for Real Time Applications FPGA architecture is proposed which performs real time video enhancement on low lighting or nonlinear lighting video. The architecture is synthesized on Virtex-6 family of FPGA (XC6VLX75T FF884). The architecture meets real time to compute 200 Mpixels/sec and is capable of enhancing 640x480 resolution frame in 172.65 µs. The proposed architecture cops with multiple level-dependent computations by using pipelining that can achieve the high throughput which is favorable for real time applications.

• NERC (National Engineering Robotics Contest) (Indigenous Line following Robot) • Simulation of Traffic Management System in Open GL. • VLSI (Layout design of 16-bits CLA) • FPGA Based System Design (Optimized FIR Filter) • Instrumentation and Measurement (Angle Measuring Instrument) • Microprocessor and Micro controller (Digital Thermometer and RTC ) • Embedded System (PIC18 based Scientific Calculator) • Electronic Circuit Design-I & II (Inverter & Charger for Inverter)

FSC Degree in Pre Engineering.